|
About the Xilinx 7-Series category
|
|
0
|
1214
|
November 16, 2016
|
|
XEM7310 RAMTester
|
|
16
|
2881
|
April 22, 2024
|
|
XEM7310MT Program Configuration flash from JTAG
|
|
2
|
184
|
December 8, 2023
|
|
ConfigureFPGAFromFlash does not work
|
|
0
|
222
|
September 27, 2023
|
|
Can I program my OK board from Vivado
|
|
1
|
250
|
August 29, 2023
|
|
How to use internal 200MHZ clock pin on the opalkelly xem7360 FPGA board?
|
|
1
|
236
|
August 7, 2023
|
|
Is there a way to debug a project using Series-7 Opall Kelly? [DEBUG]
|
|
1
|
244
|
July 28, 2023
|
|
High speed IOs in XEM 7310 board?
|
|
5
|
283
|
July 25, 2023
|
|
1Ghz clock using XEM7001?
|
|
0
|
253
|
July 20, 2023
|
|
Host interface doesn't work. Could it be broken somehow?
|
|
2
|
341
|
January 27, 2023
|
|
Requesting Help A VIVADO Project Using XEM7310 Board_IO Pin always outputting 3.3V
|
|
3
|
452
|
January 19, 2023
|
|
XEM7310 not found by Vivado
|
|
2
|
451
|
January 12, 2023
|
|
XEM7310 Bank 13 I/O-Voltage Conflict
|
|
5
|
578
|
December 6, 2022
|
|
How to use the LVDS OSC frequency in 7310
|
|
0
|
430
|
August 7, 2022
|
|
XEM7310 - Wide Temperature Range
|
|
0
|
530
|
November 16, 2021
|
|
XEM7310MT GTP Ref Clock and Sys CLK Source
|
|
4
|
1058
|
September 23, 2021
|
|
XEM7310 blinking power light (I think I broke my FPGA)
|
|
1
|
445
|
August 29, 2021
|
|
FPGA device types for XEM7350 & XEM7360
|
|
1
|
539
|
August 26, 2021
|
|
ERROR: [Synth 8-6735] 7310 okCoreHarness
|
|
3
|
945
|
May 19, 2021
|
|
Initializing and Controlling the JP header pins with verilog [XEM7001/XEM7310]
|
|
0
|
649
|
December 4, 2020
|
|
MC1 and MC2 pin 1 location on XEM7310MT
|
|
3
|
667
|
October 18, 2020
|
|
XEM7305 MIG core
|
|
2
|
812
|
July 18, 2020
|
|
XEM7305 VCC_BATT pin
|
|
0
|
700
|
January 28, 2020
|
|
OK FrontPanel HDL to AXI Master
|
|
2
|
2496
|
June 6, 2019
|
|
XEM7360 USB3.0 and Microblaze
|
|
0
|
774
|
May 17, 2019
|
|
MIG simulation on XEM7310
|
|
0
|
955
|
March 14, 2019
|
|
XEM7305 DDR3 MIG BA0 wrong pin?
|
|
1
|
1070
|
January 7, 2019
|
|
Running into "All Address/Control ports should be selected in a single bank. Address/Control selected Banks: 15. To bypass this error and proceed further for design generation" Error when generating DDR3 controller on XEM7310
|
|
0
|
815
|
January 17, 2019
|
|
Migrate from XEM6310 to 7310
|
|
1
|
1193
|
August 30, 2018
|
|
DDR3 pins for XEM7350 Board
|
|
0
|
1483
|
February 16, 2018
|