I/O on bank 13 is set fixed to 3.3 V as mentioned by OK. The extra 200-MHz oscillator is connected to bank 13 via LVDS. It has a 3.3-V LVDS output. However, the “LVDS_33” attribute was removed from 7-series FPGAs, so the I/O standard is set to “LVDS_25” instead (see RAMTester sample code).
Now there’s a conflict with other pins connected to this bank 13 (pins 64 and 66 - 76 on both expansion connectors), because all pins on bank 13 are tied officially to 2.5 V via the “LVDS_25” attribute for the oscillator input. All single-ended signals on that bank must now be set to “LVCMOS25” to not conflict with the common I/O voltage of that bank. But how bahave these I/Os? They are declared as 2.5-V types but 3.3 V is connected. Does that work?
Or does it mean, if signals are connected to bank 13 the extra 200-MHz oscillator cannot be used?
Your understanding of “because all pins on bank 13 are tied officially to 2.5 V via the ‘LVDS_25’ attribute for the oscillator input.” is incorrect. The IOSTANDARD constraint doesn’t configure/set anything in the generated bitfile. It is used by the timing engine, as well as the design rule checker (DRC) to ensure that voltage conflicts aren’t occurring with pins on the same bank.
You can read about why LVDS_25 was used at 43989. External termination is provided on the board for the clock oscillator, so an LVDS_25 input can be used with a voltage other than 2.5v. In this case, 3.3v is used.
I’m not sure why the conflict is occurring. Can you try explicitly declaring set_property DIFF_TERM FALSE [get_ports sys_clk_p] ? This should relax that DRC voltage conflict check between LVDS_25 and LVCMOS33.
Thanks for your explanation.
We migrated from XEM6310 to XEM7310 and are using 3.3-V single-ended CMOS (LVCMOS33) on bank 13. If these signals are declared as LVCMOS33, the place-and-route stops with error message “cannot mix LVDS_25 and LVCMOS33 on bank 13”.
I hope that declaring our signals LVCMOS25 (what they not are) does not affect the generate bitfile. We can live with some small descrepancies for timing analysis. (Artix 7 performs better than Spartan 6.)
What version of Vivado are you using?
set_property DIFF_TERM FALSE [get_ports sys_clk_p] should relieve the DRC check of “cannot mix LVDS_25 and LVCMOS33 on bank 13." Could you try adding this constraint to the XDC and report back on the results? Thanks
Vivado is 2022.1. I can give it a try, but the oscillator setup is predefined by OK. Why isn’t DIFF_TERM set to FALSE by OK already?
Actually setting user signals attributes to 2.5 V seems to work, too.
With DIFF_TERM set to FALSE, Vivado 2022.1 indeed accepts having LVDS_25 and LVCMOS33 in the same bank.