Xilinx 7-Series

Topic	Replies	Views	Activity
About the Xilinx 7-Series category	0	972	November 16, 2016
XEM7310 RAMTester	11	1673	January 29, 2023
Host interface doesn't work. Could it be broken somehow?	2	24	January 27, 2023
Requesting Help A VIVADO Project Using XEM7310 Board_IO Pin always outputting 3.3V	3	37	January 19, 2023
XEM7310 not found by Vivado	2	33	January 12, 2023
XEM7310 Bank 13 I/O-Voltage Conflict	5	102	December 6, 2022
How to use the LVDS OSC frequency in 7310	0	142	August 7, 2022
XEM7310 - Wide Temperature Range	0	283	November 16, 2021
XEM7310MT GTP Ref Clock and Sys CLK Source	4	563	September 23, 2021
XEM7310 blinking power light (I think I broke my FPGA)	1	246	August 29, 2021
FPGA device types for XEM7350 & XEM7360	1	315	August 26, 2021
ERROR: [Synth 8-6735] 7310 okCoreHarness	3	500	May 19, 2021
Initializing and Controlling the JP header pins with verilog [XEM7001/XEM7310]	0	401	December 4, 2020
MC1 and MC2 pin 1 location on XEM7310MT	3	470	October 18, 2020
XEM7305 MIG core	2	547	July 18, 2020
XEM7305 VCC_BATT pin	0	483	January 28, 2020
OK FrontPanel HDL to AXI Master	2	2095	June 6, 2019
XEM7360 USB3.0 and Microblaze	0	539	May 17, 2019
MIG simulation on XEM7310	0	764	March 14, 2019
XEM7305 DDR3 MIG BA0 wrong pin?	1	854	January 7, 2019
Running into "All Address/Control ports should be selected in a single bank. Address/Control selected Banks: 15. To bypass this error and proceed further for design generation" Error when generating DDR3 controller on XEM7310	0	567	January 17, 2019
Migrate from XEM6310 to 7310	1	932	August 30, 2018
DDR3 pins for XEM7350 Board	0	1249	February 16, 2018
DDR3 controller: After Pin Selection with the xdc file ,the sys_clk_p/n doesn't have the option of W11/W12(CC_P/N).(xem7310 board)	1	1841	August 14, 2017
XEM7010-A50 ISE support?	11	2210	August 5, 2017
Trouble moving from ISE to Vivado	2	1919	July 4, 2017
OK HDL to Serial Peripheral	0	1467	February 13, 2017
Xem7350 ddr mig	0	1644	February 3, 2017