|
About the Xilinx 7-Series category
|
|
0
|
865
|
November 16, 2016
|
|
XEM7310 - Wide Temperature Range
|
|
0
|
149
|
November 16, 2021
|
|
XEM7310MT GTP Ref Clock and Sys CLK Source
|
|
4
|
399
|
September 23, 2021
|
|
XEM7310 blinking power light (I think I broke my FPGA)
|
|
1
|
156
|
August 29, 2021
|
|
FPGA device types for XEM7350 & XEM7360
|
|
1
|
207
|
August 26, 2021
|
|
ERROR: [Synth 8-6735] 7310 okCoreHarness
|
|
3
|
297
|
May 19, 2021
|
|
Initializing and Controlling the JP header pins with verilog [XEM7001/XEM7310]
|
|
0
|
298
|
December 4, 2020
|
|
MC1 and MC2 pin 1 location on XEM7310MT
|
|
3
|
364
|
October 18, 2020
|
|
XEM7305 MIG core
|
|
2
|
407
|
July 18, 2020
|
|
XEM7305 VCC_BATT pin
|
|
0
|
382
|
January 28, 2020
|
|
XEM7310 RAMTester
|
|
6
|
1169
|
December 17, 2019
|
|
OK FrontPanel HDL to AXI Master
|
|
2
|
1916
|
June 6, 2019
|
|
XEM7360 USB3.0 and Microblaze
|
|
0
|
436
|
May 17, 2019
|
|
MIG simulation on XEM7310
|
|
0
|
607
|
March 14, 2019
|
|
XEM7305 DDR3 MIG BA0 wrong pin?
|
|
1
|
752
|
January 7, 2019
|
|
Running into "All Address/Control ports should be selected in a single bank. Address/Control selected Banks: 15. To bypass this error and proceed further for design generation" Error when generating DDR3 controller on XEM7310
|
|
0
|
456
|
January 17, 2019
|
|
Migrate from XEM6310 to 7310
|
|
1
|
809
|
August 30, 2018
|
|
DDR3 pins for XEM7350 Board
|
|
0
|
1145
|
February 16, 2018
|
|
DDR3 controller: After Pin Selection with the xdc file ,the sys_clk_p/n doesn't have the option of W11/W12(CC_P/N).(xem7310 board)
|
|
1
|
1734
|
August 14, 2017
|
|
XEM7010-A50 ISE support?
|
|
11
|
2091
|
August 5, 2017
|
|
Trouble moving from ISE to Vivado
|
|
2
|
1797
|
July 4, 2017
|
|
OK HDL to Serial Peripheral
|
|
0
|
1354
|
February 13, 2017
|
|
Xem7350 ddr mig
|
|
0
|
1534
|
February 3, 2017
|
