XEM7310MT GTP Ref Clock and Sys CLK Source

Xilinx 7-Series
1

@ O-K experts
I am designing a system around XEM7310MT, and now having two questions regarding the clocks;

  1. The required 125MHz GTP REF CLK for IBERT; I am assuming it is sourced from an external low-jitter 125MHz XO (through the SMA connectors on the BRK base-board for example). Would it possible to derive an useable 125MHz clock for the GTP from the onboard 200MHz sys_clk ? Admittedly, I have not done my homework on this.

  2. 200MHz onboard system clock; My system happens to also uses an 200MHz system clock. For the reason of reducing interference and having a preferred synchronism, I want to replace the 200MHz sy clk of XEM with an external 200MHz clk of my system. What is the best way of doing that ? I can think of removing the onboard XO, and soldering wires to the pads, but could not help wondering if there is a better way…
    Thanks in advance for your hep, happy holidays!

2

You would not need to solder your clock to the XO pads on the XEM7310MT – instead just bring that clock into the FPGA using the MRCC or SRCC on the expansion connector.

3

@okSupport,
One more question on this, is the on-board 200MHz XO completely independent of anything in the XEM system, like USB, or FP endpoints ? I.E., if for some reason I do end up having to replace the 200MHz XO with an 125MHz one, would that screw up anything else of XEM system ? Thanks
-HM

4

To answer your question, the 200Mhz onboard oscillator is only connected to the FPGA I/O on clock capable pins and nothing else. But you do not want to source the GTP REF CLK from anywhere but the MGTREFCLK0 or MGTREFCLK1 dedicated clock input pins on the Artix-7. Please read these Xilinx Forums posts on exactly why this is a bad idea.
https://forums.xilinx.com/t5/Ethernet/FPGA-PLL-output-as-reference-clock-for-GTP-transceiver/td-p/128744
https://forums.xilinx.com/t5/Other-FPGA-Architecture/Kintex-7-Eval-Can-the-Transceiver-reference-clock-come-from-the/td-p/809997

Essentially, if you did source the reference clock as you explain here then the jitter introduced by the MMCM/PLL and/or the routing fabric gets multiplied by however many factors needed by the PLL within the GTP to get up to the desired line speed. This magnified jitter results in bit errors on the line.

Instead bring a clean 125Mhz clock to the GTP bank’s MGTREFCLK0 or MGTREFCLK1 pins from the expansion connector. These pins are connected to pin 37, 38, 39, and 40 of MC3. You can search for these pins at the XEM7310 Pins page located here:
https://pins.opalkelly.com/pin_list/XEM7310MT

As already stated by okSupport, to sync your system under one clock, just bring that clock into the FPGA using a MRCC or SRCC clock capable pin connected to the expansion connector and clock your FPGA logic with it. You can find these clock capable pins and which expansion connector pin they are connected to at the XEM7310 Pins page as well. They will be labeled as either “_MRCC” or “_SRCC” or you can filter your search using “Display Options” and selecting “True” for “FPGA CLOCK IN”

5

Hey Michael,
Thanks for answering, your point is well taken. It seems I’d better use the dedicated clock pins, or I might have headache later on with the GTP
H.M.