Topic Replies Activity
Sample Code on XEM6310 1 April 6, 2020
Minimum BTPipeIn length 5 March 30, 2020
XEM7310 clock tolerance 3 March 23, 2020
SYZYGY carrier/pod mounting hole specification 2 February 18, 2020
Stream data from XEM7310 3 February 11, 2020
XEM7305 VCC_BATT pin 1 January 28, 2020
What is the meaning of package length and pcb length in pin reference of XEM7305? 2 January 21, 2020
okHost differences in USB3 simulation libs 4 January 2, 2020
XEM7310 RAMTester 7 December 17, 2019
Alternative Clock inputs (e.g. to XEM6310MT-LX45T via BRK6310MT breakout board) 1 December 16, 2019
okFrontPanel library causes Matlab to crash sometimes 6 December 14, 2019
DLL import location for libokFrontPanel.dylib 11 November 16, 2019
LX6 on a XEM7310 FPGA 1 October 30, 2019
ReadFromPipeOut - latency support 2 September 15, 2019
C# memory management with ReadFromBlockPipeOutX 1 September 11, 2019
Using Xilinx IP Integrator Designs with FrontPanel 1 June 4, 2019
Shuttle LX1 (XEM6006) 12V to FMC 1 July 2, 2019
25ms delay in WriteToPipeIn 7 July 1, 2019
ReadFromBlockPipeOut(...) times out on large reads 9 June 30, 2019
RegisterBridge with data loss 2 June 20, 2019
KiCad resources 1 June 16, 2019
OK FrontPanel HDL to AXI Master 3 June 6, 2019
XEM7360 VADJ values not settable 4 June 4, 2019
LabView Interface with XEM6010 and XEM6006 2 June 4, 2019
XEM7360: Setting VADJ without FrontPanel 1 June 4, 2019
Best language/API to interface with FPGA/Front Panel? 2 May 23, 2018
ISE gives error for okHostCalls.v 4 May 1, 2019
OK Reserved FPGA pins 2 May 25, 2019
XEM7360 USB3.0 and Microblaze 1 May 17, 2019
LabView FrontPanel DLL Import 10 May 5, 2019