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How long does Opal Kelly take to authenticate an additional user?
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0
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4
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June 18, 2025
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XEM7310-A200 USB power up
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0
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3
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June 18, 2025
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Timing issues with FP 1.0.6 in Vivado 2022 (default strategy) xem7310-a200
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0
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8
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June 16, 2025
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Couldn't get the "samples" to work on XEM7310-A75
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2
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18
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June 13, 2025
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Unused Differential Pins
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0
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4
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June 8, 2025
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SYZYGY Standard Peripheral Schematic Example
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2
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5
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June 8, 2025
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Failed to set user parameter 'okClk.FREQ_HZ' value '100800000' for IP 'frontpanel_0'
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0
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7
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May 27, 2025
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XEM7310-A200 Debugging via JTAG
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5
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27
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May 9, 2025
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Opal Kelly with 28 Gbit GTY
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0
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12
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May 7, 2025
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How to get data from OK host to MicroBlaze?
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3
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29
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April 22, 2025
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XEM7310, RAMTester
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1
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23
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April 15, 2025
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How to set XEM7310 I/O to 1.2v LVCMOS?
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4
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24
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April 11, 2025
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Analog low noise application
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1
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28
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March 31, 2025
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C# DLL Crashes when Power is Removed from Opal Kelly Front Panel
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10
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751
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March 20, 2025
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Unsolicited new forum account
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0
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9
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March 6, 2025
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Connections missing from board in Vivado
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1
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19
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March 6, 2025
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XEM8370 writing to pins
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1
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19
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March 5, 2025
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Read FPGA Flash on XEM7310
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2
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30
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February 8, 2025
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Help using DDR3 RAM and Clock Gen IP With XEM7310
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0
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28
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January 15, 2025
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okRegisterBridge : How to Assert regRead for Multiple Consecutive Cycles? (XEM7310)
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0
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22
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January 2, 2025
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SZG-DUALSFP Sample(s)
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9
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801
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December 30, 2024
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Too many ddr3_cke pins in xem7360 xdc file?
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0
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15
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December 26, 2024
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Can I use sys_clk pin as ordinary IO?
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0
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28
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December 24, 2024
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XEM8350 Power/Current Delivery
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4
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68
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December 11, 2024
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Python wrapper (SWIG) to roll your own?
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1
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28
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December 4, 2024
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About Host simulation; reinvoke(relaunch) & Xilinx IP simulation
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0
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18
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November 27, 2024
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Operation of "IsTriggered" function in HDL simulations
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4
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47
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November 23, 2024
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Front Panel HDL synthesis on Windows 11 fails
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3
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76
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November 8, 2024
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Automating okFilePipe method (FPGA to PC)
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1
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35
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October 10, 2024
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XEM-7310 LVDS signal
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0
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27
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October 4, 2024
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