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What is the meaning of package length and pcb length in pin reference of XEM7305?
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2
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January 21, 2020
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okHost differences in USB3 simulation libs
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4
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January 2, 2020
|
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XEM7310 RAMTester
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7
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December 17, 2019
|
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Alternative Clock inputs (e.g. to XEM6310MT-LX45T via BRK6310MT breakout board)
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1
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December 16, 2019
|
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okFrontPanel library causes Matlab to crash sometimes
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6
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December 14, 2019
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DLL import location for libokFrontPanel.dylib
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11
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November 16, 2019
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LX6 on a XEM7310 FPGA
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1
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October 30, 2019
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ReadFromPipeOut - latency support
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2
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September 15, 2019
|
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C# memory management with ReadFromBlockPipeOutX
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1
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September 11, 2019
|
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Using Xilinx IP Integrator Designs with FrontPanel
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1
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June 4, 2019
|
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Shuttle LX1 (XEM6006) 12V to FMC
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1
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July 2, 2019
|
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25ms delay in WriteToPipeIn
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7
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July 1, 2019
|
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ReadFromBlockPipeOut(...) times out on large reads
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9
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June 30, 2019
|
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RegisterBridge with data loss
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2
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June 20, 2019
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KiCad resources
|
1
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June 16, 2019
|
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OK FrontPanel HDL to AXI Master
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3
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June 6, 2019
|
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XEM7360 VADJ values not settable
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4
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June 4, 2019
|
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LabView Interface with XEM6010 and XEM6006
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2
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June 4, 2019
|
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XEM7360: Setting VADJ without FrontPanel
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1
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June 4, 2019
|
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Best language/API to interface with FPGA/Front Panel?
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2
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May 23, 2018
|
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ISE gives error for okHostCalls.v
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4
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May 1, 2019
|
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OK Reserved FPGA pins
|
2
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May 25, 2019
|
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XEM7360 USB3.0 and Microblaze
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1
|
May 17, 2019
|
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LabView FrontPanel DLL Import
|
10
|
May 5, 2019
|
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FrontPanel with Python 3.7
|
2
|
April 29, 2019
|
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hi_muxsel specification
|
3
|
April 24, 2019
|
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FrontPanel explanation
|
3
|
April 15, 2019
|
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XEM6001 not compatible with WebPack license?
|
4
|
April 28, 2016
|
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Cannot connect to FPGA: getDeviceCount() returns 0 (C/Cpp)
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2
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March 28, 2019
|
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MIG simulation on XEM7310
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1
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March 14, 2019
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