.I have a situation where I cannot see the XEM8320 in a PC after building the design per the instructions posted on the Opal-Kelly site for the PCI Express Reference Design
It would be very useful to have a guaranteed bit stream that can be used for confirmation of the XEM8320 as a PCIe endpoint.
It would be even better of the completed project was posted. But today the bit stream would be enough.
Thank You
Nick
Opal Kelly hasn’t released a specific bitfile for this example as it’s AMD’s example design, and with the proper setup, you should be able to generate it yourself. While Opal Kelly offers guidance, AMD’s documentation remains essential. Refer to Xilinx’s PCI Express DMA Drivers and Software Guide (AR65444) and DMA/Bridge Subsystem for PCI Express Product Guide (PG195) for comprehensive info. For troubleshooting, enable debug options in the DMA/Bridge Subsystem Vivado IP Core.
Hello Michael;
Thank you for your reply.
A couple questions please.
You did read that I had followed the instructions Opal-Kelly has posted the use of the AMD reference design on you site, correct?
You did read stated I cannot see the endpoint being enumerated, correct?
I have already done exactly as Opal-Kelly has instructed and built the AMD reference design Opal-Kelly have requested that I use. It did not work.
What now?
I will ask again that you please supply a known working proof bitstream to show the correct function of the XEM8320 .as a PCIe endpoint.
Given that Opal-Kelly is suppling the “official development platform for the AMD-Xilinx Artix UltraScale+ FPGA.” I do not think it is unreasonable that you have at some time tested the operation of the PCIe link and would have available the bit stream that was used to verify functionality. All that I am asking is that Opal-Kelly supply a bit stream that surely must have already been made.
Thank You
Nick
Please contact Opal Kelly support for direct assistance: [email protected]. They should be able to help.