Complications in running all the three SYZYGY ports (A,B and C) together while attaching with XEM8320

We are trying to obtain data from all the 3 ADCs(LTC226-14 bit) attached in PORT-A, B and C ports simultaneously. For that similar modules with different name are declared to solve the purpose. But the error shown by Vivado is: " [DRC MDRV-1] Multiple Driver Nets: Net adc_impl/adc_dco_impl_B/clk_out_div has multiple drivers: adc_impl/adc_dco_impl_A/mmcm_dco/CLKOUT1, and adc_impl/adc_dco_impl_B/mmcm_dco/CLKOUT1."

P.S: We have done the changes in reference design suggested by opalkelly in “Fix ADC-14 timing: Implemented MMCM phase shift in ADC sample design · opalkelly-opensource/design-resources@07f6d8e · GitHub” to make the PORT-C functional like PORT-A and B.

Have you verified the “clk_out_div” output signal (in syzygy_adc_top) is not being driven by more than one instance of adc_dco_impl?