|
About the XEM8320 category
|
|
1
|
461
|
October 20, 2022
|
|
XEM8320 power up
|
|
0
|
5
|
July 9, 2025
|
|
Connections missing from board in Vivado
|
|
1
|
20
|
March 6, 2025
|
|
XEM8320-AU25P Choosing Ethernet IP for onboard SFP cages
|
|
0
|
48
|
August 19, 2024
|
|
How to configure sma connection with fpga pins for reading external ttl pulses
|
|
0
|
219
|
January 19, 2024
|
|
Clock problem while running all the 6 channels of XEM8320 board using LTC226x-14 bit ADC
|
|
0
|
221
|
December 8, 2023
|
|
How to increase the Pipe transfer rate on USB 3.0 for XEM8320
|
|
0
|
249
|
November 10, 2023
|
|
Complications in running all the three SYZYGY ports (A,B and C) together while attaching with XEM8320
|
|
1
|
282
|
November 9, 2023
|
|
STARTUPE3 AXI QUAD SPI sample work
|
|
0
|
472
|
October 31, 2023
|
|
Setting ftdi layout_init in an OpenOCD configuration for the XEM8320
|
|
0
|
871
|
August 16, 2023
|
|
I/O planning failed while interfacing PORT C or D of LTC226x with XEM8320 board
|
|
9
|
642
|
August 8, 2023
|
|
PORT-C in XEM8320 is not giving the same waveform as PORT-A and PORT-B
|
|
1
|
455
|
August 4, 2023
|
|
Real time data transmission through PORT-A and PORT-B of XEM8320 board at a time
|
|
1
|
325
|
July 5, 2023
|
|
Program on FIFO
|
|
2
|
521
|
March 27, 2023
|
|
XEM8320 fabric_refclk_c not connected in schematics
|
|
1
|
488
|
February 6, 2023
|
|
Python is not giving any plot for adc_read.py
|
|
1
|
468
|
February 3, 2023
|
|
About okfrontpanel.dll file
|
|
1
|
402
|
February 3, 2023
|
|
SMA transceiver issue with IBERT test
|
|
0
|
539
|
December 21, 2022
|
|
XEM8320-AU25P FPGA in the loop using Matlab
|
|
0
|
466
|
September 30, 2022
|
|
XEM8320-AU25P : Are the PINs on SYZYGY interface configurable?
|
|
1
|
485
|
September 12, 2022
|
|
XEM8320-AU25P datasheet needed
|
|
4
|
620
|
September 9, 2022
|
|
Xilinx Artix UltraScale+ FPGA development board with FMC
|
|
1
|
712
|
March 22, 2022
|