Program on FIFO

We have implemented the sample design of ADC on board XEM8320. Now, to perform any additional operation on this project we are trying to understand the verilog coding of the sample ADC program (As we are beginners). How the following functions are reading data from FIFO:

okWireOR # (.N(1)) wireOR (okEH, okEHx);
okTriggerIn trigIn53 (.okHE(okHE), .ep_addr(8’h40), .ep_clk(adc_data_clk), .ep_trigger(ep40trig));
okWireIn wire00 (.okHE(okHE), .ep_addr(8’h00), .ep_dataout(ep00data));
okPipeOut pipeOuta0 (.okHE(okHE), .okEH(okEHx[ 0*65 +: 65 ]), .ep_addr(8’ha0), .ep_read(ep_read), .ep_datain(pipea0_data));

Hello and welcome!

I recommend starting by reading through our documentation here: Introduction - Opal Kelly Documentation Portal. That will give you some background on everything and leads into to our API and HDL documentation.

After that, feel free to reach back out if you have any additional questions!

Thanks for your suggestion. Could you tell whether any modification is possible on the existing “Sample ADC program” using XEM8320? As I am struggling to do so.