XEM8320-AU25P FPGA in the loop using Matlab

XEM8320
1

Hello,

We need to do FiL for the new (FPGA XCAU25P-2FFVB676E) board. The board customization needs some info for the FPGA IO interfacing using JTAG and I couldn’t find the answer in the online data sheet.

  1. The needed info are as the following:
  • “Sum of IR length before”
  • “Sum of IR length after”

Also there are other advanced options for the User[1…4] Instruction and JTAG Clock frequency (MHz).

  1. For the board basic info, is there a specific “Reset pin number” and what is the active level ?
  2. I want also please to confirm that the SYS clk shall be connected to pins T24 & U24.

Thanks