Port width mismatch for port 'ep_datain' in okWireOut

Hi there,
I have the following Component declaration in my VHDL for okWireOut:

component okWireOut
    port (
        okHE        : in    std_logic_vector(112 downto 0);
        okEH        : out   std_logic_vector(64 downto 0);
        ep_addr     : in    std_logic_vector(7 downto 0);
        ep_datain   : in    std_logic_vector(31 downto 0)

Which agrees with declaration found in okLibrary.vhd from FrontPanel. The Vivado does not seem to be happy with it giving me the following error:

[Synth 8-549] port width mismatch for port ‘ep_datain’: port width = 32, actual width = 16 [“C:/Users/…/sources_1/new/top_elroy_max_concept.vhd”:219]

Obviously, I cannot look at the actual module declaration inside okWireOut.v because it is an encrypted file.
Any help would be appreciated.


Hello and welcome!

It sounds like some FrontPanel HDL might have gotten mixed up when importing them into your project. What device are you using? I would reinstall FrontPanel from Opal Kelly Pins and then reimport the FrontPanel HDL for your device from the FrontPanelHDL folder in the FrontPanel installation. That way, we can be sure the FrontPanel install will be clean and have the correct files.

Hello hayden,

I am using an Artix UltraScale+ device. Thanks for the suggestion, I will give it a try.


I uninstalled OpalKelly completely and then re-installed it again (version 5.3.1), copied “C:\Program Files\Opal Kelly\FrontPanelUSB\FrontPanelHDL\XEM8320-AU25P\Vivado-2021” folder to my project “…\sources_1\imports” and re-ran the synthesis. Unfortunately, I got the same error. Any suggestions?

It still seems like you may have the wrong okWireOut.v imported… I would check the okWireOut.v’s path to make sure it is the one you expect. I can confirm by building the counters.vhd sample that I am not able to recreate this issue on my side.

I deleted the imported folder (Vivado-2021) from my project and re-imported again with no success.
File location of “okWireOut.v”: C:/Program Files/Opal Kelly/FrontPanelUSB/FrontPanelHDL/XEM8320-AU25P/Vivado-2021.
Is it possible to get just the okWireOut.v file, the one which you used for the project so I could troubleshoot my system?

I can’t redistribute those files, apologies.

My only other hypothesis is that Vivado may be caching something incorrectly, or otherwise misbehaving. Could you please restart Vivado and build the Counters.vhd sample for the XEM8320-AU25P? It is in the Samples folder.

You should also check the counters.vhd file to ensure that you are instantiating the okHost and the wireout module correctly.

Looks like I found what was wrong. For the context, I am working with the provided “EthernetMac” example. The topmost file is written in Verilog that I needed to convert to VHDL. Apparently, the line (and other similar)

okWireOut ep27 (.okHE(okHE), .okEH(okEHx[ 7 * 65 +: 65 ]), .ep_addr(8’h27), .ep_datain(MACDestinationAddress_1[47:32]));

is not equivalent to

ep27 : okWireOut port map (okHE => okHE, okEH => okEHx(8 * 65-1 downto 65 * 7), ep_addr => x"27", ep_datain => MACDestinationAddress_1(47 downto 32));

Instead, you need to manually concatenate the signal to get expected 32 bit wide bus:

ep27 : okWireOut port map (okHE => okHE, okEH => okEHx(8 * 65-1 downto 65 * 7), ep_addr => x"27", ep_datain => x"0000" & MACDestinationAddress_1(47 downto 32));

And the error messages from Vivado are not explicit enough to pinpoint the issue.

Thank you for the support!