Vivado sim error, XEM7360 okCoreHarness : error generated

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Hi,

I ran into an error. [XSIM 43-3253] /imports/Vivado/okCoreHarness.v, line 14893. Verilog alias ports are not supported in mixed language simulation. I am using vivado 2019.2.

Can anyone please help me?

Thanks,
Zhaoyang