Vivado sim error, XEM7360 okCoreHarness : error generated

FrontPanel
1

Hi,

I ran into an error. [XSIM 43-3253] /imports/Vivado/okCoreHarness.v, line 14893. Verilog alias ports are not supported in mixed language simulation. I am using vivado 2019.2.

Can anyone please help me?

Thanks,
Zhaoyang

2

I’m having the same problem. Did you solve it?

3

This type of error is caused by using the encrypted FrontPanel sources to simulate with instead of the simulation sources found in the Simulation folder of your FrontPanel installation.

More information is available here: