Too many ddr3_cke pins in xem7360 xdc file?

Xilinx 7-Series
1

Hi,

I’m using the external SDRAM on an xem7360. I generated the MIG according to OpalKelly’s instructions and I’m using OpalKelly’s provided xdc files, however, the generated mig only has one CKE pin whereas the XDC file has 2. Furthermore, the documentation here suggests that there’s only one CKE pin.

Below is a snippet from the provided XDC file

set_property PACKAGE_PIN AC12 [get_ports {ddr3_cke[0]}]
set_property PACKAGE_PIN AA12 [get_ports {ddr3_cke[1]}]
set_property SLEW FAST [get_ports {ddr3_cke[*]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[*]}]

Which of these is correct? Are there two CKE pins or one CKE pin?

Thanks,
John