ERROR: [Synth 8-6735] 7310 okCoreHarness


I’m having the above error when attempting to compile a new bitfile via non-project workflow tcl script. The full error:
ERROR: [Synth 8-6735] net type must be explicitly specified for ‘l233aa7bee2c916d8fab1c72e4c9ae55d’ when default_nettype is none [/home/cblam/hdl/okCoreHarness.v:63]

Curiously the design compiles fine within vivado without any changes.

Has anyone seen this before and/or have suggestions to debug?

That is strange. The fact that it works in Vivado may be an indicator that your workflow tcl script may be the issue. Try to double check your tcl scripts to make sure they are sound. If you still cannot move past this issue, post a snippet of your tcl scripts and maybe I can spot something out.

Also, which version of the HDL sources are you using?

I believe I’ve figured it out!

My tcl script was missing this key line before initaiting synth_design:
update_compile_order -fileset [current_fileset]

Great! And feel free to let me know if it is still an issue.

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