Xilinx 7-Series
| Topic | Replies | Views | Activity | |
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OK FrontPanel HDL to AXI Master
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2 | 2749 | June 6, 2019 |
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XEM7360 USB3.0 and Microblaze
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0 | 882 | May 17, 2019 |
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MIG simulation on XEM7310
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0 | 1039 | March 14, 2019 |
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XEM7305 DDR3 MIG BA0 wrong pin?
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1 | 1160 | January 7, 2019 |
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Running into "All Address/Control ports should be selected in a single bank. Address/Control selected Banks: 15. To bypass this error and proceed further for design generation" Error when generating DDR3 controller on XEM7310
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0 | 914 | January 17, 2019 |
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Migrate from XEM6310 to 7310
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1 | 1304 | August 30, 2018 |
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DDR3 pins for XEM7350 Board
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0 | 1568 | February 16, 2018 |
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DDR3 controller: After Pin Selection with the xdc file ,the sys_clk_p/n doesn't have the option of W11/W12(CC_P/N).(xem7310 board)
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1 | 2269 | August 14, 2017 |
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XEM7010-A50 ISE support?
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11 | 2699 | August 5, 2017 |
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Trouble moving from ISE to Vivado
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2 | 2782 | July 4, 2017 |
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OK HDL to Serial Peripheral
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0 | 1745 | February 13, 2017 |
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Xem7350 ddr mig
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0 | 1943 | February 3, 2017 |