Dear all,
I have a question about the ddr3 controller on xem7310.
I want to generate this memory controller using the MIG IP in Vivado. After Pin Selection with the xdc file, the sys_clk_p/n doesn’t have the option of W11/W12(CC_P/N).
the part about sys_clk_p/n in xdc file:
set_property IOSTANDARD LVDS_25 [get_ports {sys_clk_p}]
set_property PACKAGE_PIN W11 [get_ports {sys_clk_p}]
set_property IOSTANDARD LVDS_25 [get_ports {sys_clk_n}]
set_property PACKAGE_PIN W12 [get_ports {sys_clk_n}]
I want to know how to solve this problem?
PS: Vivado 2016.3
Thanks