I am having trouble with the choice of IO pins. I wish to use high-speed IO pins to transfer and receive data (as fast as possible). I picked up an IO pin (pin AA15, referenced by Pins: XEM7310) that looks like a GPIO, but the fastest frequency I can achieve is only around 10 MHz. Beyond this frequency, it seems the driving ability is so limited that the output waveform starts corrupting.
My questions are:
What is the max frequency of the IO? Which IO pins should I choose? How should I configure the IO pins in the constraint file? Would you please point me to a more detailed IO document other than the pin reference webpage?
Please refer to the AMD-Xilinx Artix-7 documentation. There is extensive documentation available for each I/O standard supported and what the capabilities are.
I do check the documentation. According to the DC switching characteristic document AMD Adaptive Computing Documentation Portal, it seems the output delay is only ~2ns with LVCMOS18 IO standard. However, I can never achieve similar speed even if I maximize the driving strength and select slew type to be fast. Now the fastest data rate is only around 10 MHz with zero load on the board.
Will this issue be related to the impedance matching on the board? Has anyone tested the max data rate of the IO? Any input will be greatly appreciated!
What I did is simply divide the 200 MHz system clock sys_clk using the clock wizard IP and assign the divided clock to an IO. Here’s the constraints related to the IO:
It runs into severe signal integrity issues in this case. It seems that the FPGA’s output driver is unable to handle this frequency with only the probe’s cap present.
