Initializing and Controlling the JP header pins with verilog [XEM7001/XEM7310]

I am having a lot of trouble figuring out how to configure my FPGA to use the JP header pins on the board.

My desire is to be able to send the FPGA commands through the existing okWireIn framework and use the data sent over to control the JP header pins on the board. Specifically, I would like to be able to actuate the signals coming out of header FPGA pins J1, J3, K2, K1 on header JP2 and pin B9 on. header JP3.

How do I set this up in my Verilog? I have found clear examples on everything except this part. I see pin definitions in my XDC file on Vivado but cannot access any of these values in my Verilog code. I would appreciate any advice on how to set this functionality up.

I previously posted this under the Verilog/VHDL folder and got no responses.