Hi,
I have a XEM7310-A200 and I am trying to simulate a design that uses Xilinx’s MIG for DDR3. I have downloaded the RTL model for the DRAM chips from Micron. In the simulation, the DRAM model prints a lot of timing violation errors.
I had done this before for Xilinx’s board (VC707) and their example design was very useful in getting this set up. Does anyone have an example design for XEM7310-A200 (or a related board)?
Mehul