Running into "All Address/Control ports should be selected in a single bank. Address/Control selected Banks: 15. To bypass this error and proceed further for design generation" Error when generating DDR3 controller on XEM7310

Xilinx 7-Series
1

Hi,

I am trying to generate my own MIG (Version 4.2) controller in Vivado v2018.3 (64-bit) but in the wizard, when trying to assign pin locations, I run into the problem of “All Address/Control ports should be selected in a single bank. Address/Control selected Banks: 15. To bypass this error and proceed further for design generation”. I know that the setting is based on an older version of the core but wondering if there is a workaround for the newer version.

Regards,
Arman