Python Not Finding OK
Problems with okFrontPanel.dll
Problem with linking Xilinx cells instantiated in okHost.vhd
IsFrontPanelEnabled() ----> "False" (w/ Python & "First" Example)
FrontPanel Missing Panel Buttons
FrontPanel for RaspBerry
Migrate from XEM6310 to 7310
DDR3 pins for XEM7350 Board
DDR3 controller: After Pin Selection with the xdc file ,the sys_clk_p/n doesn't have the option of W11/W12(CC_P/N).(xem7310 board)
Spartan-6 USB 3.0 Modules
XEM6310: pin for SDRAM Controller is already in use by okHost
Asynchronous FIFO generate
XEM6310 sometimes stuck
Cyclone IV USB 3.0 Modules
Data acquisition from a TI 100MSPS ADC via HSMC
Placement of okHostMicrocode.hex
How to define(or set) the initial value of FPGA(cyclone-IV) pins when power-on
Spartan-3 USB 2.0 Modules
Migrating from XEM6010 and XEM6310
xem3005 synthesis problem?
EZ-USB FX2LP for XEM3010 FPGA. USB Signaling Speed
Spartan-6 USB 2.0 Modules
I want VCCAUX to be 2.5-volts with XEM6010-LX150
USB transfer breaks after some time
okTriggerIn single-cycle pulse guaranteed?
Spartan-6 PCI Express Module
Is XEM6110 foot-print compatible with 6310?
FP support for Xilinx Spartan-6 PCIe endpoint?
Can I use Sonnet HBA cards with this XEM6110?
Virtex-5 USB 2.0 Module
DDR2 SDRAM interface doesn't work?
Unique serial number on PCB for XEM5010
VHDL / Verilog Discussion
Transferring Data using Verilog and Python
Verilog Initial begin does not execute in simulation
Difference between Bit File and UCF File
Working with the microblaze on the XEM7010-A50
Error in implement design
Common problems migrating from XEM6001 to XEM6010
Discussion about this forum, its organization, how it works, and how we can improve it.
Generic open source library for programming opal kelly devices
VHDL ramtest XEM3010
LabView FrontPanel DLL Import
Creating a forum to discuss Vivado/AXI with OK HDL endpoint development
Optiphase WTG Question
FrontPanel on Android devices?