Hello.
I’m looking for a more detailed account of the FPGA pins to DDR3 pins on the XEM 7350 board. The pin connections are exact for the FPGA pin, but DDR3 pin specifies only the signal name. Some of the signal descriptions are not fully accounted i.e.
DDR3 Pin: DM0 -> FPGA Pin: AD4
DDR3 Pin: DM1 -> FPGA Pin: V11
However, on the DDR3 data sheet there is just LDM and UDM signal descriptions. If I had the exact pin mapping I would be able to determine where those signals are going to make my design more exact.
Thank you!
-Mitch