|
Ringing on FPGA output
|
|
1
|
1134
|
May 15, 2007
|
|
Xilinx ISE with Synplify Synthesizer
|
|
0
|
1151
|
May 15, 2007
|
|
SDRAM clock line
|
|
2
|
950
|
May 11, 2007
|
|
Bank 3 power
|
|
3
|
963
|
May 9, 2007
|
|
4MB SPI Serial Flash
|
|
1
|
932
|
May 2, 2007
|
|
Initialization problems
|
|
2
|
1328
|
April 29, 2007
|
|
Suggestions
|
|
6
|
1677
|
April 25, 2007
|
|
GCLK IOB Standard
|
|
1
|
1041
|
April 23, 2007
|
|
Frontpanel component OkBTPipeIn
|
|
1
|
927
|
April 20, 2007
|
|
Transfer Speeds
|
|
1
|
855
|
April 17, 2007
|
|
DESTester example with Visual C++ 2005
|
|
7
|
1395
|
April 16, 2007
|
|
Help implementing design to work with Python as well as FrontPanel
|
|
1
|
943
|
April 10, 2007
|
|
Help implementing design to work with Python as well as FrontPanel
|
|
0
|
777
|
April 10, 2007
|
|
DESTester example with Visual C++ 2005
|
|
0
|
934
|
April 10, 2007
|
|
xem3005 pinout mismatch
|
|
1
|
1107
|
April 6, 2007
|
|
Using dll with c#
|
|
3
|
1146
|
March 30, 2007
|
|
Post-Translate simulation problems
|
|
0
|
807
|
March 30, 2007
|
|
Achieving perfect match between the XEM3010 and its motherboard
|
|
1
|
899
|
March 30, 2007
|
|
Sdram
|
|
1
|
936
|
March 29, 2007
|
|
LabView 8.2 DLL importer
|
|
0
|
876
|
March 23, 2007
|
|
False triggering
|
|
2
|
925
|
March 23, 2007
|
|
Block-Throttled Pipes and FP-3 Feedback
|
|
1
|
915
|
March 23, 2007
|
|
Connecting USB through JP2/3?
|
|
2
|
1273
|
March 22, 2007
|
|
ResetFPGA?
|
|
1
|
1056
|
March 20, 2007
|
|
Python help
|
|
1
|
828
|
March 20, 2007
|
|
SDRam Controller under FP-3
|
|
1
|
849
|
March 14, 2007
|
|
ISE: Web Pack or full version?
|
|
1
|
1176
|
March 14, 2007
|
|
Work with Floating point core in Xilinx Web Pack 8.1i
|
|
0
|
1069
|
March 8, 2007
|
|
Pipe test Example not working
|
|
2
|
1490
|
March 8, 2007
|
|
Issues downloading bit file.Getting okFILE_ERROR
|
|
5
|
1276
|
March 7, 2007
|