I have DDR data and and a single ended CMOS clock at 1.8v that I need to get into the Spartan FPGA on the XEM3010. I see that I can use the VCCO_x voltages in the JP2 and JP3 connectors to set the Spartan IO voltage banks 2,3,6,and 7. Is there a way to set bank 0 or 1 voltage so I can use a GCLK input for source synchronous clocking? It seems like the only way the Xilinx tools will let me bring the clock into the FPGA is on a GCLK, but the GCLK bank voltage seems to be 3.3V.
Lane