Pipe test Example not working

FrontPanel
1

Hi,
have just received the board, and am trying out the samples first, but have a problem where the sample application “PipeTest” fails when the ‘test pipe in / out’ buttons are pressed.

Also in the Fifo controls section, the Write to Fifo-in seems to generate some data, but the read FIFO-in always returns FFFF

here is the output from the Pipetest.exe.

FrontPanel DLL built: Jan 23 2007 20:33:37
FPGA configuration complete.
WriteToPipeIn(…) failed.
Bytes written: 0.
Write: 21078 milliseconds (0.049747 MB/sec) (0.397979 Mb/sec)
WriteToPipeIn(…) failed.
Read: 10031 milliseconds (0.104534 MB/sec) (0.836268 Mb/sec)
BPI Write: 2329 84BE 6CE1 AED6 9052
BPI Read: 0xFFFF (status: 0xFFFF)
BPO Write: 0x1649
BPO Read: 0xFFFF 0xFFFF

Any help gratefully received.
Chris

2

I believe the pipe test requires the RAM expansion module to be attached.

3

Nope, this was our goof.

The PipeTest does not require the RAM module attached.

The problem is that the Verilog sample has a pin mapping constraint commented out. You need to uncomment the “button” signal and rename it “button”. This was done in the VHDL version of the sample, but we missed the Verilog version. As such, the bitfile is also wrong – button is mapped as the Xilinx tools best saw fit.

Additionally, the compiled sample needs to be modified to remove the “BufferedPipe” stuff as these have been removed from the sample. These fixes will be in our next release.