SDRAM clock line

The wiring on the carrier board adds a 3" stub to the SDRAM clock line, which results in poor signal integrity. Is there a resistor jumper on the XEM3005 that disconnects the SDRAM clock from pin J3-78?
If not could you recommend a good place to cut the trace on the module to achieve the same thing?
Thanks, Klaus

I am a little confused about how the SDRAM clock routing is handled.
I know PLL LCLK1 goes to FPGA pin A8 and is also connected to R29.
If R29 is stuffed the clock does through to J3-78.
From the UCF file I can see that FPGA pin A9 is sdram_g_clk which I would guess is connected to R28.
This however does not match the documentation in the XEM3005-UM.pdf document on page 13 where it says thatSYS_CLK1is fanned out to both FPGA pin A9 and the SDRAM when R28 is REMOVED.
I would think this should either read A8 or R28 has to be inserted (in addition to R29).
On the next page under “System Synchronous from JP3” it states that the clock from JP3 is fanned out to both FPGA pin A8 and the SDRAM. This does not seem to make sense either and I think should read A9.
The “Source Synchronous” section is the only one that appears to be correct.
Please clarify.
Thanks, Klaus


I think the diagram needs to be updated to clarify one point:

  • SYS_CLK1 is routed to FPGA A8 at all times.

There was a typo and because of the similarities in the numbers involved, I can see how this can get incredibly confusing. There was also a change from our prototype to production board which apparently didn’t get fully reconciled with the documentation. We’re reviewing this right now.

At the bottom of p13, change “pin A9, GCLK8” to “pin A8, GCLK8”.
At the top of p14, change “pin A8, GCLK7” to “pin A9, GCLK7”.
In the Source Synchronous section, it should read pin A9 (GCLK7).

Thanks for pointing this out. I’m surprised it hadn’t been caught yet!