I have some problem with the SDRAM controller in VHDL. Some times reading from ram or writing to a ram is problematic.
Can you please give me more information about the constraints that are writen in VHDL? I don’t know how to embed them to VHDL.
I would be very appritiate if you can give me the exact directios to write the 6 synthesis constraints for placing IOB attributes on the SDRAM signals that you mentioned before to claude.boulard for the SDRAM controller written in vhdl.
Best Regards,



Please have a look at the “Xilinx Constraints Guide” available from the Xilinx website. There are a number of different ways to express the constraints you may need and all will depend on how you build your project.

Also, we only provide a Verilog version of the SDRAM controller and some constraints are already written into the Verilog there. It may often be the case that your HDL gets larger and requires additional constraints to meet timing.