Work with Floating point core in Xilinx Web Pack 8.1i


#1

i have the following proceed.
in Xilinx webPac 8.1i Add flaoting point Core and also add its component and its instation. there is no error.
i have made a three signal of 32 bit and assign value to Core A , B and Result signal.
now the problem is i am reading the value for A and B signal from RegdataIn and then directly result of core is Assign to Result Signal and give to RegDataOut. but the Result i am getting is not Correct.
here i am showing my code…

---- this is Component Map
component floatip
port (
a: IN std_logic_VECTOR(31 downto 0);
b: IN std_logic_VECTOR(31 downto 0);
operation_nd: IN std_logic;
operation_rfd: OUT std_logic;
clk: IN std_logic;
sclr: IN std_logic;
result: OUT std_logic_VECTOR(31 downto 0);
invalid_op: OUT std_logic;
divide_by_zero: OUT std_logic;
rdy: OUT std_logic);
end component;

—Declare Signal for Process
signal SFloatA : std_logic_vector(31 downto 0);
signal SFloatB : std_logic_vector(31 downto 0);
signal SFloatResult : std_logic_vector(31 downto 0);
signal SNewData:std_logic;
signal SReadyForData:std_logic;
signal SInvalid_Op:std_logic;
signal SDivide_Error:std_logic;
signal SReady:std_logic;

signal SConstR : std_logic_vector(31 downto 0);
signal SInitP : std_logic_vector(31 downto 0);
signal SDivResutl : std_logic_vector(31 downto 0);

–Regdata In For Core A and B Signal
when X"3000" => SConstR(7 downto 0) SConstR(15 downto 8) SConstR(23 downto 16) SConstR(31 downto 24) SInitP(7 downto 0) SInitP(15 downto 8) SInitP(23 downto 16) SInitP(31 downto 24)
STempRegDataOut RegDataOut RegDataOut RegDataOut SFloatA,
b => SFloatB,
operation_nd => SNewData,
operation_rfd => SReadyForData,
clk => CLK,
sclr => RST,
result => SFloatResult,
invalid_op => SInvalid_Op,
divide_by_zero => SDivide_Error,
rdy => SReady
);

Helllo sir please give me answer what is the Wrong
.
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GINOYA HASMUKH M.
(Software Engg.) Cell:-9427630119
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