Help implementing design to work with Python as well as FrontPanel

Hi. I have a project ready to be implemented onto the XEM3001v2 board, but I do have few questions. First, I’m trying to use the data ports available on the Host Interface Pin , how would I instantiate to enable it as both Input/Output? Second, how can I map the ports to use with my project? I understand that the xem3001.ucf contains the constraint files necessary for the project, so I add that file as the design/implementation file. What else do I need to do to map it? Lastly, what is necessary to be instantiated in Python to work in conjunction with FrontPanel? Please help.


Have you taken a look at the samples included with the FrontPanel software CD? They were installed with FrontPanel and include HDL (Verilog and VHDL) as well as host code (C, Java, Python) for some of the examples.

Specifically, you may want to take a look at the DESTester sample and Counters samples.