VHDL / Verilog Discussion

Topic	Replies	Views	Activity
[DRC REQP-1578] Unsupported MMCME2_ADV	2	914	April 4, 2023
XEM7310 Clock Speed in XDC	3	763	October 12, 2022
XEM6310-LX45 Help with Bidirectional Control	1	544	October 20, 2021
Initializing and Controlling the JP header pins with verilog [XEM7001]	0	602	November 10, 2020
Transferring Data using Verilog and Python	1	2525	June 23, 2017
Verilog Initial begin does not execute in simulation	0	2170	July 2, 2014
Difference between Bit File and UCF File	0	2211	April 2, 2014
Problem VHDL help in code please	0	2017	January 24, 2014
beginner question	0	1791	November 7, 2013
beginner question	0	1577	November 7, 2013
OK HOST - bus interfacing - vhdl vs verilog - different implementation - question	3	3409	November 5, 2013
Verilog beginner question	1	1868	November 5, 2013
Outputting Clock	0	1876	August 15, 2013
VHDL Help - Controlling A Stepper Motor Driver	0	2403	July 26, 2013
ActivateTriggerIn Simulation task	1	1997	May 8, 2013
VHDL: Register File with Eight 8-bit Registers	0	3343	February 22, 2013
URGENT, Need Help in Verilog code!	0	1640	July 7, 2012
Trouble with ISE 13.2 and wireIn/wireOut ngc files	3	1880	February 2, 2012
Need guideline for NRZI output related question	0	1577	September 11, 2011
Visualize your design with Robei	0	1563	April 26, 2011
Need some vhdl help	1	1560	December 10, 2010
Factors req to choose VHDL or Verilog	2	1537	November 30, 2010
Source files encrypiton	0	1433	February 9, 2010
Verilog Constructs	2	1843	November 18, 2009
Uart	0	1916	March 8, 2009
C to Verilog	0	1508	December 16, 2008
OK and synplicity synthesis tool	1	1781	December 12, 2008
A new FPGA design tutorial	0	1524	December 8, 2008
8051 with watchdog timer	0	1671	July 14, 2008
Expression unsynthesizable	1	1488	June 17, 2008