VHDL / Verilog Discussion

Topic	Replies	Views	Activity
[DRC REQP-1578] Unsupported MMCME2_ADV	2	1066	April 4, 2023
XEM7310 Clock Speed in XDC	3	861	October 12, 2022
XEM6310-LX45 Help with Bidirectional Control	1	567	October 20, 2021
Initializing and Controlling the JP header pins with verilog [XEM7001]	0	622	November 10, 2020
Transferring Data using Verilog and Python	1	2573	June 23, 2017
Verilog Initial begin does not execute in simulation	0	2189	July 2, 2014
Difference between Bit File and UCF File	0	2215	April 2, 2014
Problem VHDL help in code please	0	2033	January 24, 2014
beginner question	0	1795	November 7, 2013
beginner question	0	1596	November 7, 2013
OK HOST - bus interfacing - vhdl vs verilog - different implementation - question	3	3465	November 5, 2013
Verilog beginner question	1	1895	November 5, 2013
Outputting Clock	0	1892	August 15, 2013
VHDL Help - Controlling A Stepper Motor Driver	0	2439	July 26, 2013
ActivateTriggerIn Simulation task	1	2014	May 8, 2013
VHDL: Register File with Eight 8-bit Registers	0	3357	February 22, 2013
URGENT, Need Help in Verilog code!	0	1642	July 7, 2012
Trouble with ISE 13.2 and wireIn/wireOut ngc files	3	1906	February 2, 2012
Need guideline for NRZI output related question	0	1583	September 11, 2011
Visualize your design with Robei	0	1573	April 26, 2011
Need some vhdl help	1	1576	December 10, 2010
Factors req to choose VHDL or Verilog	2	1556	November 30, 2010
Source files encrypiton	0	1440	February 9, 2010
Verilog Constructs	2	1856	November 18, 2009
Uart	0	1923	March 8, 2009
C to Verilog	0	1515	December 16, 2008
OK and synplicity synthesis tool	1	1793	December 12, 2008
A new FPGA design tutorial	0	1534	December 8, 2008
8051 with watchdog timer	0	1679	July 14, 2008
Expression unsynthesizable	1	1501	June 17, 2008