VHDL / Verilog Discussion

Topic	Replies	Views	Activity
XEM6310-LX45 Help with Bidirectional Control	1	136	October 20, 2021
Initializing and Controlling the JP header pins with verilog [XEM7001]	0	258	November 10, 2020
Transferring Data using Verilog and Python	1	1979	June 23, 2017
Verilog Initial begin does not execute in simulation	0	1822	July 2, 2014
Difference between Bit File and UCF File	0	1810	April 2, 2014
Problem VHDL help in code please	0	1654	January 24, 2014
beginner question	0	1420	November 7, 2013
beginner question	0	1215	November 7, 2013
OK HOST - bus interfacing - vhdl vs verilog - different implementation - question	3	2773	November 5, 2013
Verilog beginner question	1	1475	November 5, 2013
Outputting Clock	0	1484	August 15, 2013
VHDL Help - Controlling A Stepper Motor Driver	0	1984	July 26, 2013
ActivateTriggerIn Simulation task	1	1616	May 8, 2013
VHDL: Register File with Eight 8-bit Registers	0	2748	February 22, 2013
URGENT, Need Help in Verilog code!	0	1206	July 7, 2012
Trouble with ISE 13.2 and wireIn/wireOut ngc files	3	1468	February 2, 2012
Need guideline for NRZI output related question	0	1210	September 11, 2011
Visualize your design with Robei	0	1189	April 26, 2011
Need some vhdl help	1	1188	December 10, 2010
Factors req to choose VHDL or Verilog	2	1137	November 30, 2010
Source files encrypiton	0	1062	February 9, 2010
Verilog Constructs	2	1452	November 18, 2009
Uart	0	1405	March 8, 2009
C to Verilog	0	1159	December 16, 2008
OK and synplicity synthesis tool	1	1412	December 12, 2008
A new FPGA design tutorial	0	1065	December 8, 2008
8051 with watchdog timer	0	1300	July 14, 2008
Expression unsynthesizable	1	1116	June 17, 2008
Dividision by repeted multiplication	2	1065	May 22, 2008
VHDL not seeing output port	1	1043	May 20, 2008