XEM6310-LX45 Help with Bidirectional Control
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1
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136
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October 20, 2021
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Initializing and Controlling the JP header pins with verilog [XEM7001]
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0
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258
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November 10, 2020
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Transferring Data using Verilog and Python
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1
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1979
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June 23, 2017
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Verilog Initial begin does not execute in simulation
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0
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1822
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July 2, 2014
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Difference between Bit File and UCF File
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0
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1810
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April 2, 2014
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Problem VHDL help in code please
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0
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1654
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January 24, 2014
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beginner question
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0
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1420
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November 7, 2013
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beginner question
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0
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1215
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November 7, 2013
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OK HOST - bus interfacing - vhdl vs verilog - different implementation - question
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3
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2773
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November 5, 2013
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Verilog beginner question
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1
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1475
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November 5, 2013
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Outputting Clock
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0
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1484
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August 15, 2013
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VHDL Help - Controlling A Stepper Motor Driver
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0
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1984
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July 26, 2013
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ActivateTriggerIn Simulation task
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1
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1616
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May 8, 2013
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VHDL: Register File with Eight 8-bit Registers
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0
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2748
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February 22, 2013
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URGENT, Need Help in Verilog code!
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0
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1206
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July 7, 2012
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Trouble with ISE 13.2 and wireIn/wireOut ngc files
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3
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1468
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February 2, 2012
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Need guideline for NRZI output related question
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0
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1210
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September 11, 2011
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Visualize your design with Robei
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0
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1189
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April 26, 2011
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Need some vhdl help
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1
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1188
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December 10, 2010
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Factors req to choose VHDL or Verilog
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2
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1137
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November 30, 2010
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Source files encrypiton
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0
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1062
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February 9, 2010
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Verilog Constructs
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2
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1452
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November 18, 2009
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Uart
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0
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1405
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March 8, 2009
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C to Verilog
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0
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1159
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December 16, 2008
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OK and synplicity synthesis tool
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1
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1412
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December 12, 2008
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A new FPGA design tutorial
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0
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1065
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December 8, 2008
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8051 with watchdog timer
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0
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1300
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July 14, 2008
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Expression unsynthesizable
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1
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1116
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June 17, 2008
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Dividision by repeted multiplication
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2
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1065
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May 22, 2008
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VHDL not seeing output port
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1
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1043
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May 20, 2008
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