Verilog Constructs


I’m looking at the “PipeTest.v” file. There are a couple of verilog constructs here that I’m unfamiliar with and can’t seem to find in my book or on the net. If you could help explain these I would be very appreciative.

wire [1718-1:0] ok2x;
okWireOR # (.N(18)) wireOR (ok2, ok2x);
okWireOut ep20 (.ok1(ok1), .ok2(ok2x 0
17 +: 17 ]), .ep_addr(8’h20), .ep_datain({16{tick}}));

]What does the "[017 +: 17]" particularly the +: do in the statement “.ok2(ok2x 0*17 +: 17 ]”

*]In the part “.ep_datain({16{tick}})” the {} are confusing. It almost looks like a concatenation but with 2 sets of brackets.

*]And finally, in the okWireOr instantiation, does the # (.N(18)) just update the parameter in the okWireOr module?

Thanks very much for you help


  1. This is a fancy way to do bit selection without having to add. 017 evaluates to 0 and we select the next 17 bits, i.e. [0:16]. 117 evaluates to 17 and we select the next 17 bits so [1*17 +: 17] is equivalent to [17:33].

  2. {16{x}} just replicates ‘x’ 16 times. The effect is a 16-bit bus with all “x” signals fanned out.

  3. Yes, # is a way to specify parameters to a Verilog module.

I’m not entirely sure when these constructs were introduced into Verilog, but they may be somewhat recent additions. (2001 or later)

Thanks very much for your feedback.

So is the "[117 +: 17]" bus reversed? It looks like the expression
wire [17
18-1:0] ok2x;
would have been from [MSB:LSB] and the “[1*17 +: 17]” would be [LSB:MSB]. So connecting the 2 would seem to reverse the bus.

Thanks for the help