Transferring Data using Verilog and Python


I am using the transferring data example provided by Opal Kelly but when I put the Verilog code into Xilinx, I receive the following errors. I am not sure how to fix them. Please help.

// Circuit wires
wire fifowrite;
wire fiforead;
wire [15:0] datain;
wire [15:0] dataout;
wire reset;
wire [15:0] wireout;

//Circuit behavior
assign reset = wireout[0];

// Xilinx Core IP Generated FIFO
FIFO_16bit fifo(

// FrontPanel module instantiations
okWireIn wire10(

okPipeIn pipe80(
.ok2(ok2x[0*17 +: 17]),

okPipeOut pipeA0(
.ok2(ok2x[1*17 +: 17]),

ERROR:HDLCompiler:718 - “F:/transferringdata/transferringdata.v” Line 34: Port connections cannot be mixed ordered and named
ERROR:HDLCompiler:45 - “F:/transferringdata/transferringdata.v” Line 35: ok1 is not a function
ERROR:HDLCompiler:24 - “F:/transferringdata/transferringdata.v” Line 35: ok1 expects 0 arguments
ERROR:HDLCompiler:69 - “F:/transferringdata/transferringdata.v” Line 36: is not declared.
ERROR:HDLCompiler:69 - “F:/transferringdata/transferringdata.v” Line 44: is not declared.
ERROR:HDLCompiler:598 - “F:/transferringdata/transferringdata.v” Line 3: Module ignored due to previous errors.

Thank you.


The online examples are only intended to demonstrate the FrontPanel interface portion of a design accomplishing a specific task. As such, these are not full verilog modules that will synthesize properly. These examples still require some extra code around the FrontPanel interface to create a full module. Similarly, the software side generally does not have all of the required “#include” statements to fully compile the code either.

If you are looking for more complete projects that use the FrontPanel interface you may want to look through the samples available in the FrontPanel distribution (in Windows this is located in the FrontPanel installation folder, typically at C:\Program Files\Opal Kelly).