[DRC REQP-1578] Unsupported MMCME2_ADV

I have a XEM7310MT and this is my first project in Vivado vs legacy ISE. I have straightened out the differences in the constraints file but have gotten stuck at this 1578 error. The W19 pin on the FGG484 is a MRCC so it should be a clock capable IO. This happens if I use the Vivado IP or what comes with the 5.2.11 drivers. Only thing that I have touching the okCLK is a FIFO.

After some reading and head banging, I found something with IBUFG vs BUFG. Xilinx UG472 pg78 does not mention IBUFG as a valid CLKIN1 input to a MMCME2_ADV. A lot of the graphics show an IBUFG input but the text does not. If I only modify the okLibrary to a BUFG, Vivado can implement it (generate a bitfile). While I have the code working with this mod, I am concerned I have to change Opal Kelly’s code to get it to work.

What did I do to my project that I have to modify the stock OK code from a IBUFG to a BUFG?
BUFG should be used for an internal clock and not used for an external clock, right?
Can someone explain this to me like a 5 year old on why this works?

Appendix data

line 75 okLibrary.vhd:
hi_clk_bufg : IBUFG port map (I=>okUH(0), O=>okUH0_ibufg);

Full error Text:
“[DRC REQP-1578] Input clock driver: Unsupported MMCME2_ADV connectivity. The signal TheMux/FrontP/inst/okHI/okUH[0] on the TheMux/FrontP/inst/okHI/mmcm0/CLKIN1 pin of TheMux/FrontP/inst/okHI/mmcm0 with COMPENSATION mode ZHOLD must be driven by a clock capable IO.”

After a quick test, I am reminded that it is an assumption that compiling means working. BUFG generates a bitfile that doesn’t talk.

I was routing the okUH though an if_rising(sys_clk) in the routing to the Frontpanel Block. This would cause the compiler to make okUH clocked by the sys_clk. Made the routing async and everything is working. PEBCAK.