i wrote this code for a simple counter , 1 to 9. Apparently, it compiles properly including pin assignments but when i go to program, nothing show up on there. Ive tried other vhdl projects and they program fine. any ideas?
ENTITY counter IS
PORT (CLOCK : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
ARCHITECTURE mylogic OF counter IS
signal count : std_logic_vector (25 DOWNTO 0);
signal a : std_logic;
signal D : std_logic_vector (3 DOWNTO 0);
BEGIN PROCESS (CLOCK)
IF (CLOCK’EVENT AND CLOCK = ‘1’) THEN
count <= not ((not D(1) and D(2)) or D(3) or (D(1) and not D(2)) or (D(2) and not D(0)));
using quartus 2 for a cyclone II board.