Outputting Clock


I’m new to using opalkelly FPGAs. In the past I’ve used a spartan-3e FPGA to try to output 4 phase shifted clock signals.
The project that I would like to complete is outputting 4 phase shifted saw tooth clocks. I’m trying to tackle the problem in small steps. The first thing that I would like to accomplish is outputting 4 phase shifted clock signals to spaces on JP2 and JP3.

With a Xilinx spartan 3e a DCM was required to multiply the clock signal to achieve the proper clock frequency for each phase, however DCM is not compatible with a opalkelly XEM6001 spartan-6. Do you have any recommendsations on how to phase shift 4 clock signals and rout them to output pins? Also do i have to use ODDR2 to output the clock to specific pins? Additionally I would like to set each channel to achieve 32Mhz.

Using ISE 14.6
Opal Kelly XEM6001