XEM6310-LX45 Help with Bidirectional Control

VHDL / Verilog Discussion
1

Hello,

I’m struggling much more than I expected in implementing INOUT signals properly with verilog HDL and unfortunately the examples they have with this function do not have complete HDL interface for me to follow.

I’m intending to use python to control and read the pin states from the XEM6310-LX45 and have had no problem with using INPUT and OUTPUT signals with the okWireIn and okWireOut blocks. I’ve also been able to control these fine with the Python. I’ve run into a wall when I tried adding in the INOUT signals which keep erroring out when I try to generate a bit file in Xilinx.

Does anyone have an example (simplistic or otherwise) that they could share to properly setup the HDL with the okWire blocks for a bidirectional I/O? I’ve included the HDL I’m working with as well if anyone wants to point out where I’m going wrong.

default_nettype none timescale 1ns / 1ps

module bidi(
input wire [4:0] okUH,
output wire [2:0] okHU,
inout wire [31:0] okUHU,
inout wire okAA,
output wire [3:0] signal_in,
input wire [3:0] signal_out,
inout wire [3:0] signal_inout,
output wire direction,
output wire [7:0] led
);

// Target interface bus:
wire okClk;
wire [112:0] okHE;
wire [64:0] okEH;

// Endpoint connections:
wire [31:0] ep00wire;
wire [3:0] signal_reg;

assign led = ~ep00wire[7:0];

// inputs
assign signal_inout = direction ? signal_reg : 4’bZ;
assign signal_reg = signal_inout;

// Instantiate the okHost and connect endpoints.
wire [65*3-1:0] okEHx;
okHost okHI(
.okUH(okUH),
.okHU(okHU),
.okUHU(okUHU),
.okAA(okAA),
.okClk(okClk),
.okHE(okHE),
.okEH(okEH)
);

okWireOR # (.N(3)) wireOR (okEH, okEHx);
okWireIn led00 (.okHE(okHE), .ep_addr(8’h00), .ep_dataout(ep00wire));
okWireIn si01 (.okHE(okHE), .ep_addr(8’h01), .ep_dataout({direction,signal_in}));
okWireIn si02 (.okHE(okHE), .ep_addr(8’h02), .ep_dataout(signal_inout));
okWireOut so20 (.okHE(okHE), .okEH(okEHx[ 065 +: 65 ]), .ep_addr(8’h20), .ep_datain(signal_out));
okWireOut so21 (.okHE(okHE), .okEH(okEHx[ 165 +: 65 ]), .ep_addr(8’h21), .ep_datain(signal_in));
okWireOut so22 (.okHE(okHE), .okEH(okEHx[ 2*65 +: 65 ]), .ep_addr(8’h22), .ep_datain(signal_inout));

endmodule

2

This is a circular assignment. You probably won’t get too far with this:

This is the first result when googling “verilog bidirectional assignment”:
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/ver-bidirec.html

There are a lot of other HDL examples online and in the reference materials for Intel and Xilinx FPGAs that could be very useful if you’re new to HDL.