Verilog beginner question

Hi all,

Complete novice asking a question here.

I’m just curious about using the calculated output of a pure combinational logic block, in a vector dereference. What I mean is, is this a legitimate way to derefence a block of memory on the core?

reg [7:0] mem [1023:0];
reg [7:0] someValue;

addrOffs = (y * 2) + x;
someValue = mem[addrOffs];

I guess the question is, does addrOffs need time to settle before “mem” can validly be indexed with this value? The gist would be to use something similar to this kind of array dereference in a single clock, and then retrieve “someValue” after it has been validly applied on the next clock, ie, one clock, calculate “addrOff”, dereference “someValue”. Next clock, use someValue.

Is this correct understanding, or “addrOffs” definitely needs to be stabilised prior to using it as an index? I was just wondering how the decoding of the flop to use would handle a changing value during settle time.



Your question is actually more of a circuit design question than it is a Verilog question.

Your method of dereferencing the memory or flops is fine. There will be a certain time for the combinational logic to settle. Part of the job of a synthesis tool is to check much of this timing for you, and report to you whether your circuit will have any trouble settling in time. “In time” really means by a certain amount of time before the next clock (called the setup time). The output of the logic (in this case an index to a memory) must be stable (stop changing) during this setup time (of the flop or memory), or you will get undetermined results. You can imagine if you chose a clock which was very low frequency (long period) there would be plenty of time to settle, while a high frequency clock would give you very little time to settle. Different memories in different technologies will have different setup times, which ultimately limits how fast your design can go.