beginner question

Hi all,
I am a beginner in Verilog, and I am wondering if this code is going to work and if I can put nest if statement inside the case statement

module semester(
input [3:0]w,
input Clock,
input switch,
output first,
output second,
output third,
output fourth
);
reg [2:0] y;
reg [1:0] counter;
initial begin
counter=00;
y=110;
end
parameter [2:0] A = 3’b000, B = 3’b001, C = 3’b010, D= 3’b011,E=3’b100,F=3’b101,G=3’b110,H=3’b111;
always@ (posedge Clock)begin
case (y)
A:
if(w==0001|switch==1) begin
y<=D;
counter=00;
end
endcase

thank you