Problem VHDL help in code please

The figure 1 depicts the internal structure of the MAC circuit. This synchronous circuit is a
Multiplier And Accumulator.

The input and output ports of the circuit are described hereafter:

? The A and B inputs are 8-bit wide buses carrying unsigned integer values.

? The S output is an 8-bit wide bus carrying unsigned integer values.

? The M input is an single bit input.

? Though the rst and clk lines/inputs exist (as the MAC is a synchronous circuit), they are not shown in the figure to alleviate its complexity.

During normal operation (with the M input set to 0), the circuit calculates the cumulative value Pt At ∗ Bt (where At and Bt denote the values of A and B at clock cycle t. When the M
is set to ?1?, the cumulative value (and intermediate operande values are all reset to 0.

The goal in this problem is to write a behavioral model of this MAC circuit at the RTL level
(hence, a synthetisable model) that only uses a single process in its internal architecture.

anyone can help me please to solve this :stuck_out_tongue: