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Connections missing from board in Vivado
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1
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78
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March 6, 2025
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XEM8370 writing to pins
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1
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88
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March 5, 2025
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Read FPGA Flash on XEM7310
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2
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124
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February 8, 2025
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Help using DDR3 RAM and Clock Gen IP With XEM7310
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0
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92
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January 15, 2025
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okRegisterBridge : How to Assert regRead for Multiple Consecutive Cycles? (XEM7310)
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0
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77
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January 2, 2025
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SZG-DUALSFP Sample(s)
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9
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942
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December 30, 2024
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Too many ddr3_cke pins in xem7360 xdc file?
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0
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46
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December 26, 2024
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Can I use sys_clk pin as ordinary IO?
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0
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74
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December 24, 2024
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XEM8350 Power/Current Delivery
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4
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145
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December 11, 2024
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Python wrapper (SWIG) to roll your own?
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1
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70
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December 4, 2024
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About Host simulation; reinvoke(relaunch) & Xilinx IP simulation
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0
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98
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November 27, 2024
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Operation of "IsTriggered" function in HDL simulations
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4
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143
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November 23, 2024
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Front Panel HDL synthesis on Windows 11 fails
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3
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208
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November 8, 2024
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Automating okFilePipe method (FPGA to PC)
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1
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92
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October 10, 2024
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XEM-7310 LVDS signal
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0
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76
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October 4, 2024
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XEM8320-AU25P Choosing Ethernet IP for onboard SFP cages
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0
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111
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August 19, 2024
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XEM7310 bank 35 voltage issue
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0
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64
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August 6, 2024
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XEM7010-A50 RAMTester Failing (Reading 0s)
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0
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68
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August 1, 2024
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Migrating from XEM6310 to XEM7310-A200
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0
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79
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July 25, 2024
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Vivado sim error, XEM7360 okCoreHarness : error generated
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2
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823
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July 23, 2024
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Failed to claim USB interface: Device or resource busy (error 16) under Ubuntu
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0
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238
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July 10, 2024
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Port width mismatch for port 'ep_datain' in okWireOut
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7
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298
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June 26, 2024
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Using ISE14.7 with an XEM7310-A200
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1
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126
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June 12, 2024
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Multiple XEM 7310 boards on Ubuntu 20 LTS
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0
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153
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June 4, 2024
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[C++] Incorrect number of devices shown
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3
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1977
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May 28, 2024
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Different okHost Ports for Simulation vs. Implementation XEM8350
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2
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722
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May 24, 2024
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okClk not toggling on xem7320
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0
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151
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May 15, 2024
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Recommended method to Transfer data from PC to FPGA - USB3.0
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2
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444
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April 23, 2024
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XEM7310 RAMTester
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16
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3758
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April 22, 2024
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Login Issues Fixed!
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0
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153
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April 17, 2024
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