Hi, all.
I am currently using the Vivado environment to perform simulations based on the method described in this documentation.
Following the steps in the documentation, I set up sim.v and sim_tf.v and ran sim_vivado.bat through the Vivado TCL shell. This worked as expected, and the waveform for the simulation was displayed without any issues.
Q1. How to reinvoke the simulation
After modifying the source HDL, such as sim.v and sim_tf.v, is there an easier way to reinvoke (relaunch) the simulation so that the simulate with updated HDL?
In the GUI, the relaunch menu is disabled as shown below. Currently, I close the waveform viewer and re-run sim_vivado.bat, which is an inconvenient process.
Q2. Simulation with Xilinx Core IP
In examples provided by Opal Kelly, such as Transferring Data or Setting and Getting Multiple Registers, some use Xilinx Core IP.
I am trying to simulate these examples to get familiar with the functionalities of Opal Kelly. However, when I run sim_vivado.bat using the previously mentioned method, it fails to load the modules and throws an error.
Is there a way to simulate source HDL that include Xilinx Core IP?
Would it work if I follow the method described in this documentation?
Initially, I attempted the simulation using that method but failed, so I switched to the method using sim.v and sim_tf.v
Any help would be very appreciated.
Thanks.