Flash interface for XEM6001 vs. XEM7001
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4
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759
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March 24, 2022
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Shuttle LX1 (XEM6006) 12V to FMC
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0
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898
|
July 2, 2019
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hi_muxsel specification
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2
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2327
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April 24, 2019
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XEM6001 not compatible with WebPack license?
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3
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2512
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April 28, 2016
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Failing okHostIN_grp timing constraint on xem6310
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3
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960
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February 5, 2019
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I want VCCAUX to be 2.5-volts with XEM6010-LX150
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0
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1118
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August 8, 2018
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USB transfer breaks after some time
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0
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1216
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June 22, 2018
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okTriggerIn single-cycle pulse guaranteed?
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0
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1172
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March 23, 2018
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Problem with "first" example,
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0
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2017
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March 1, 2018
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Piping in data to block RAM
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1
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1520
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January 23, 2018
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FLASH FPGA configuration and data storage
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19
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4157
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October 30, 2017
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Write and read on ddr2 sdram for xem6010-lx45
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1
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1609
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April 7, 2017
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XEM6010-LX45 Problem with “Triplicated Data” Output from RAM FIFO
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1
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2126
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September 16, 2016
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BTPipeOut module for wrong version of Spartan-6 on XEM6001
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1
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1920
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June 18, 2016
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XEM6010 Powered Using External 3.3V Supply
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0
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2337
|
May 17, 2016
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Multiple PipeOut - Piping Out of Order?
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1
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2244
|
June 26, 2015
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Migrating from XEM3010 to XEM6010 - differential signal pair compatibility
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2
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2349
|
April 30, 2015
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Timing Simulation w/ Frontpanel Stimulus
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|
1
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2182
|
April 7, 2015
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Python 3.4 ImportError: DLL load failed
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3
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4614
|
April 4, 2015
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SPI flash on XEM6001 for general storage
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1
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2183
|
February 12, 2015
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Multiplexing inputs into ADC and reading the digitized outputs with XEM6010
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3
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2531
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February 12, 2015
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XEM6010 JP1, JP2 and JP3 discrepancy
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1
|
2584
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November 17, 2014
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XEM6001 - okBTPipeOut buffering
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6
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3268
|
November 13, 2014
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Is there a reset input from the board that is available to RTL?
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1
|
2530
|
September 24, 2014
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Clock frequency in Shuttle LX-1 FPGA
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3
|
2460
|
September 8, 2014
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Python 3.3 ImportError: DLL load Failed: The specifiied module could not be found
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1
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5830
|
July 18, 2014
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Ubuntu 12.04 (32 bit) with FrontPanel 4.4.0
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2
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2247
|
July 16, 2014
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Are EEPROM bits accessable from the FPGA?
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5
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2514
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July 10, 2014
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Typical USB Transfer Latency
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3
|
2498
|
June 20, 2014
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Matlab DLL call time
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3
|
4125
|
April 23, 2014
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