Multiple PipeOut - Piping Out of Order?


#1

Hi All,

I’m working on an XEM 6001 to send data to my computer via USB 2.0 from Nblock blocks of RAM, each of which has 512 32-bit-wide addresses to which I can save data, through Nblock PipeOuts (i.e. one PipeOut for each block RAM).

Here, each address contains an entire ‘data point’: the number of clock cycles since the FPGA started running its state machine (i.e. time value) (18 bits) concatenated with some other information (14 bits). Currently, Nblocks = 32, though I encounter the problem that I’m having with as few as 8 blocks of RAM.

Namely, the data outputted to the computer and saved/printed using Python 2.7 has some points with time values that are multiples of 512 (+/- 1 or 2) that are out of order. For example, I may find that that 1023rd, 2049th, and 2560th data points have time values that are discontinuous with the rest of the data, like below:

Steps) time values

  1. 5
  2. 20
  3. 35
  4. 95
  5. 105
  6. 25
  7. 115
  8. 125

I am wondering if this could be a result of incorrect use of okPipeOut (code below) or is more likely a problem in my state machine?

Sincere thanks in advance!


// Instantiate output RAM blocks
genvar k;
generate
    for (k=0; k <= N_blocks; k=k+1) begin: rams
        RAMB16_S18_S36 ram_O (.CLKA(ti_clk), .SSRA(start), .ENA(1’b1),
                            .WEA(1’b0), .ADDRA(ramO_addrA[k]),
                            .DIA(16’b0), .DIPA(2’b0), .DOA(pipeO_data[k]), .DOPA(),
                            .CLKB(clk1), .SSRB(start), .ENB(1’b1),
                            .WEB(ramO_write[k]), .ADDRB(ramO_addrB),
                            .DIB(ramO_din), .DIPB(4’b0), .DOB(), .DOPB());
    end
endgenerate

// Instantiate the okHost and connect endpoints.
wire [17*(3 + N_blocks)-1:0]  ok2x;
okHost okHI(
  .hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout), .ti_clk(ti_clk),
  .ok1(ok1), .ok2(ok2));

okWireOR # (.N(3 + N_blocks)) wireOR (ok2, ok2x);

okWireIn        wi00(.ok1(ok1),                                .ep_addr(8’h00), .ep_dataout(start));

okTriggerOut ep60(.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8’h60), .ep_clk(clk1), .ep_trigger(ep60trig));

genvar l;
generate
    for (l=0; l <= N_blocks; l=l+1) begin: outpipes
        okPipeOut epA (.ok1(ok1), .ok2(ok2x[ (2+l)*17 +: 17 ]), .ep_addr(8’ha0+l), .ep_read(pipeO_read[l]), .ep_datain(pipeO_data[l]));
    end
endgenerate

endmodule


#2

First of all, does your design meet timing?

It looks like your use of okPipeOut is reasonable, but it’s not clear that the issue is on the “output” side of the memory. Are you certain that the input side is completed before readout? I notice that your input side and output side of the memory are on two different clock domains.

Have you tried to simulate this design? What about ChipScope? Both tools are very valuable at rooting out this sort of issue.