I’m having trouble with a specific application. My hardware looks like this:
–> One 16-to-1 multiplexer with independently programmable input channels
–> The output of the mux is connected to the input of a 14-bit, parallel ADC, and each of the ADC bits [13:0] is wired up to the XEM6010 module.
–> ADC sampling rate ~1 MHz, slow enough to avoid settling issues with the multiplexed ADC system.
I am trying to multiplex all 16 inputs in real-time and to capture all chunks of data in one data stream. My test case is to ground the first 15 the inputs (which I can effectively do on my PCB), and bias the last input with a DC voltage (e.g. 3.2 Volts).
In my Verilog HDL, I have a so-called wrapper module which switches the multiplexer select lines (mux_sel[3:0]) on one positive edge of a clk, and subsequently samples the ADC on the following positive edge. I am using a simple 64k, 16-bit wide FIFO to pipe data out; for simplicity, I use a PipeOut to read data from my relatively large FIFO block. Top-level code is listed here for reference: https://www.dropbox.com/s/bf5sj5w210kt1mo/FPGAcontrol_top_level.txt?dl=0. The ‘realtime_mux_counter_2’ module simply guarantees that selecting the proper mux select lines never coincides with sampling the ADC, as described before.
I am using Python to communicate with the Opal Kelly, but I am trouble recovering the data in a bitstream. With my contrived example from before, I expect something like this to appear in the computer (units in Volts): [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.2]. This does not happen reliably.
Does any one have any insight as to what may be going wrong? Any feedback or further comments are appreciated.