How can I know (and control) the frequency of the external clock signal of the Shuttle LX-1 FPGA?
This is documented in the Shuttle LX1 User’s Manual. The external clock frequency is fixed at 48 MHz. If you require different frequencies, the FPGA has on-board PLL and DCM capabilities to synthesize additional clock frequencies.
Many thanks. May be I have not the right manual; the one I have is the “ShuttleLX1-UM.pdf” created on 13 Oct 2011, and has not this info.
Is there any new and more complete one?
The PINS reference for the XEM6006 only seems to include the FMC connector pins, not all the pins that are generated in the UCF file. For example, the auto-generated UCF file contains a sys_clk input on FPGA pin T8, but this is not mentioned in the block diagram, user’s manual, or PINS reference table.
It’s been over a year since the original poster asked the question, but the current version of the manual still does not have the sys_clk information. It is not “documented in the Shuttle LX1 User’s Manual” as the reply stated.
Also, the package is shown as FGG256 in the block diagram, and the part is listed as XC6SLX16-2FGG. For the XC6SLX16 the correct package is FTG256, not FGG. It can cause some minor confusion when setting up the Xilinx project.