Failing okHostIN_grp timing constraint on xem6310


#1

TIMEGRP “okHostIN_grp” OFFSET = IN 2 ns VALID 2 ns BEFORE “okUH[0]” RISING;

–fails with this result

  • TIMEGRP “okHostIN_grp” OFFSET = IN 2 ns V | SETUP | 1.651ns| 0.349ns| 0| 0
    ALID 2 ns BEFORE COMP “okUH(0)” " | HOLD | -1.179ns| | 4| 4445
    RISING"

This timing constraint always seems to fail when I’m building my design, even if I comment out my entire design it still fails.


#2

Are you sure that you have the correct FPGA part selected for your project?


#3

Fairly sure, this is what it says at the start of PaR

par -w -intstyle ise -ol high -mt off platform_top_map.ncd platform_top.ncd
platform_top.pcf

Constraints file: platform_top.pcf.
Loading device for application Rf_Device from file ‘6slx150.nph’ in environment C:\EDA_Tools\Xilinx\14.7\ISE_DS\ISE.
“platform_top” is an NCD, version 3.2, device xc6slx150, package fgg484, speed -2


#4

It was something to do with trying to timing ignore any paths between the okClk and other clocks in my system

TIMESPEC TS_00_TIG=FROM “okHostClk” TO “okSysClk” TIG;
TIMESPEC TS_01_TIG=FROM “okHostClk” TO “CLK_52MHz” TIG;
TIMESPEC TS_02_TIG=FROM “okHostClk” TO “CLK_26MHz” TIG;
TIMESPEC TS_03_TIG=FROM “okHostClk” TO “CLK_25MHz” TIG;
TIMESPEC TS_04_TIG=FROM “okHostClk” TO “CLK_24MHz” TIG;