USB transfer breaks after some time


we try to acquire data from an external device and read it to the PC using a BTPipe.
a) The external devices delivers 20 MBits/s.
b) 8 incoming bits are converted to 2 bytes (1 data byte and one status byte)
c) These 2 bytes are pushed into a fifo (16 wide 28 words deep)
d) A programmable full signal is used to generate the ready signal of the BTPipe
e) The full signal is typical set to 64 words (16 bit = 1 word)
f) Read operation to the pipe is done with blocksize = 128 (bytes) and a large amount of bytes is read
The basic idea was that the pipe starts if there are enough data in the fifo and there is still space for more data.

This approach works for some data (1-4 Seconds running) and then there are missing data. The whole transfer is done by a single DLL-Command.

Is there anything, which we should try?

The important part of the code:

assign ep60trig[0] = (spi_cs_n[2:1] == 2’b01) ? 1’b1 : 1’b0; // trigger if cs_n goes high

assign epA0pipe = (adc_test_mode) ? fifo_dataout : {7’d0, fifo_empty, fifo_dataout[7:0]};
assign fifo_rd = (fifo_empty) ? 1’d0 : (epA0read | epA1read);

fifo_spi_receiver_progFull16 input_fifo (
.clk(ti_clk), // input clk
.rst(~reset_n), // input rst
.din({spi_shift2,spi_shift}),// input [15 : 0] din
.wr_en(fifo_load), // input wr_en
.rd_en(fifo_rd), // input rd_en
.dout(fifo_dataout), // output [15 : 0] dout
.full(fifo_full), // output full
.empty(fifo_empty), // output empty

// Instantiate the okHost and connect endpoints.
wire [17*9-1:0] ok2x;
okHost okHI(
.hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout), .ti_clk(ti_clk),
.ok1(ok1), .ok2(ok2));

okWireOR # (.N(5)) wireOR (ok2, ok2x);

okWireIn wi00(.ok1(ok1), .ep_addr(8’h00), .ep_dataout(ep00wire)); // BASIC config
okWireIn wi01(.ok1(ok1), .ep_addr(8’h01), .ep_dataout(ep01wire)); // BT pipe config
okWireIn wi07(.ok1(ok1), .ep_addr(8’h07), .ep_dataout(ep07wire)); // UART speed config
okWireIn wi08(.ok1(ok1), .ep_addr(8’h08), .ep_dataout(ep08wire)); // MSbyte start bit of UART; LSbyte clock frequency
okWireIn wi09(.ok1(ok1), .ep_addr(8’h09), .ep_dataout(ep09wire)); // Number of system clock cycles until clock off!
// this wire is currently not used
okWireOut wo20(.ok1(ok1), .ok2(ok2x[ 017 +: 17 ]), .ep_addr(8’h20), .ep_datain(ep20wire));
// start transfer to CDC
okTriggerIn ti40(.ok1(ok1), .ep_addr(8’h40), .ep_clk(ti_clk), .ep_trigger(ep40trig));
// signal rising edge of cs_n
okTriggerOut to60(.ok1(ok1), .ok2(ok2x[ 1
17 +: 17 ]), .ep_addr(8’h60), .ep_clk(ti_clk), .ep_trigger(ep60trig));
// read bytes from fifo
okPipeOut piA0(.ok1(ok1), .ok2(ok2x[ 217 +: 17 ]) , .ep_addr(8’hA0), .ep_datain(epA0pipe), .ep_read(epA0read));
okBTPipeOut piA1(.ok1(ok1), .ok2(ok2x[ 3
17 +: 17 ]), .ep_addr(8’hA1), .ep_datain(epA0pipe), .ep_read(epA1read), .ep_blockstrobe(epA1strobe), .ep_ready(epA1ready));
// write byte to fifo for uart
okPipeIn pi90(.ok1(ok1), .ok2(ok2x[ 4*17 +: 17 ]), .ep_addr(8’h90), .ep_dataout(ep90pipe), .ep_write(ep90write));