Piping in data to block RAM


#1

To whom it may concern,

I am interested in piping binary data (a string of ones and zeros) from a text file to my FPGA logic. To accomplish this task, I have been following along with the Transferring Data SDK Example (https://www.opalkelly.com/examples/transferring-data/). Instead of piping data out to my PC using okPipeOut, I would like to store the output data from the FIFO into a 2-D RAM. Then, I envision using an assign statement to concatenate 16-bit chunks of data into a wire with a longer bit-depth. I liken this to reading from the RAM, like so:

always @(posedge ti_clk or posedge reset)
begin
if (reset)
begin
addr_counter <= 5’d0;
end
else if (fifowrite == 1’b1)
begin
ramdatain[addr_counter] <= dataout;
addr_counter <= addr_counter + 1’b1;
end
end

wire [(16*16)-1:0] leddata;
assign leddata = {ramdatain[0], ramdatain[1], ramdatain[2], ramdatain[3], ramdatain[4]};

Does this sound like a reasonable approach? I have not gotten this to work yet, so I am definitely open to suggestions.

Cheers,
Scott T.


#2

I’m using the XEM6001, by the way. Thanks!