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What is the part number of the Ferrite for XEM7310?
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1
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379
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January 9, 2023
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XEM7320 J3 Port ADC
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1
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539
|
August 24, 2022
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Any plans for supporting Mac M1/M2 ARM processors?
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1
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480
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August 21, 2022
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Configure from system flash and reset
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0
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443
|
August 18, 2022
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Power XEM7310MT +VDCIN
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1
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475
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August 16, 2022
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ECM1900 Board can't build because of # of PS8's
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2
|
513
|
July 13, 2022
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Use of Block-Throttled Pipe Out
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3
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1096
|
July 12, 2022
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|
XEM7310 Pipe Out, Trigger Out
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1
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750
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May 26, 2022
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WriteToPipeIn and ReadFromPipeOut using python doesnt seem to work?
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3
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1161
|
March 11, 2022
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Change pin drive strength in XEM7360
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1
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508
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February 5, 2022
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Sample Matlab Code to call to DLL
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0
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783
|
November 11, 2021
|
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Software Reset of FPGAs possible?
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|
14
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1515
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August 30, 2021
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Implementation Issue When Migrating from XEM3001v2 to XEM7001
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|
1
|
588
|
July 16, 2021
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Expected USB 3.0 bandwidth with multiple devices
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|
1
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661
|
May 20, 2021
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If I damage my XEM7310
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2
|
647
|
April 2, 2021
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Issue loading okFrontPanel library in 64-bit MATLAB R2020b on Ubuntu Linux 20.04
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1
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828
|
March 26, 2021
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okTriggerIn and false_path constraints
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|
0
|
670
|
January 4, 2021
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ADS1675REF board support file request
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|
1
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645
|
December 24, 2020
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XEM7310 I/Os pulled up during configuration, but shouldn't be
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1
|
645
|
November 13, 2020
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Cannot import ok Python library
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2
|
2897
|
October 30, 2020
|
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Stream data from XEM7310
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|
3
|
1181
|
April 30, 2020
|
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Where is the documentation for the FrontPanel scripting?
|
|
10
|
2858
|
April 29, 2020
|
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Minimum BTPipeIn length
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|
4
|
2530
|
March 30, 2020
|
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XEM7310 clock tolerance
|
|
2
|
722
|
March 23, 2020
|
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DLL import location for libokFrontPanel.dylib
|
|
10
|
2104
|
November 16, 2019
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LX6 on a XEM7310 FPGA
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|
0
|
710
|
October 30, 2019
|
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ReadFromPipeOut - latency support
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|
1
|
964
|
September 15, 2019
|
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C# memory management with ReadFromBlockPipeOutX
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|
0
|
767
|
September 11, 2019
|
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Using Xilinx IP Integrator Designs with FrontPanel
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|
0
|
761
|
June 4, 2019
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XEM7360: Setting VADJ without FrontPanel
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|
0
|
703
|
June 4, 2019
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