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Sample Matlab Code to call to DLL
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0
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759
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November 11, 2021
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Software Reset of FPGAs possible?
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14
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1348
|
August 30, 2021
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Implementation Issue When Migrating from XEM3001v2 to XEM7001
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1
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556
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July 16, 2021
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Expected USB 3.0 bandwidth with multiple devices
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1
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609
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May 20, 2021
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If I damage my XEM7310
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2
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633
|
April 2, 2021
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Issue loading okFrontPanel library in 64-bit MATLAB R2020b on Ubuntu Linux 20.04
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1
|
810
|
March 26, 2021
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okTriggerIn and false_path constraints
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0
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630
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January 4, 2021
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ADS1675REF board support file request
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1
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629
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December 24, 2020
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XEM7310 I/Os pulled up during configuration, but shouldn't be
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1
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612
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November 13, 2020
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Cannot import ok Python library
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2
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2791
|
October 30, 2020
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Stream data from XEM7310
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3
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1094
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April 30, 2020
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Where is the documentation for the FrontPanel scripting?
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10
|
2733
|
April 29, 2020
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Minimum BTPipeIn length
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4
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2470
|
March 30, 2020
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XEM7310 clock tolerance
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2
|
691
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March 23, 2020
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DLL import location for libokFrontPanel.dylib
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10
|
2010
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November 16, 2019
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LX6 on a XEM7310 FPGA
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0
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695
|
October 30, 2019
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ReadFromPipeOut - latency support
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1
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948
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September 15, 2019
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C# memory management with ReadFromBlockPipeOutX
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0
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746
|
September 11, 2019
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Using Xilinx IP Integrator Designs with FrontPanel
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0
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751
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June 4, 2019
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XEM7360: Setting VADJ without FrontPanel
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0
|
688
|
June 4, 2019
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OK Reserved FPGA pins
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1
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690
|
May 25, 2019
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Hope everyone have a nice holiday
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0
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846
|
December 26, 2018
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Installing usb drivers for xem3005 under windows 10
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0
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1364
|
November 6, 2018
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Blocking wait for trigger
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0
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1012
|
October 28, 2018
|
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Python Not Finding OK
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|
5
|
2405
|
August 21, 2018
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Problems with okFrontPanel.dll
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0
|
1099
|
June 26, 2018
|
|
Problem with linking Xilinx cells instantiated in okHost.vhd
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0
|
1293
|
June 8, 2018
|
|
What is the part name of power regulator in XEM 7310?
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1
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1347
|
May 23, 2018
|
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Synchronization with external clock
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|
0
|
1111
|
April 13, 2018
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How to setup 1.2V control signals by using XEM6010-LX45
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1
|
1094
|
March 28, 2018
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