What GPT quad does the XEM7320 75T and 200T connect to the transceiver port? Is Opal Kelly ever going to supply hardware support, in the form of a simple demo, for this pod?
You’ll have to look at the XEM7320 Pins Reference, and cross reference that information with the Artix-7 FPGA Package Device Pinout Files. Here are the pinout files for the XEM7320-A75T and the XEM7320-A200T. SYZYZY Port C’s RX0p signal is connected to FPGA pin B8. Searching FPGA pin B8 in Xilinx’s Pinout file reveals it belongs to GTP bank 216.
Although Opal Kelly doesn’t supply a SFP example design at this time, there are plenty of example designs involving SFP available online. All that would be required is to constrain it to the SZG-DUALSFP connected to Port C on the XEM7320. You could put together this XDC constraints file utilizing the “Pinout” section at SZG-DUALSFP’s Documentation.
You could plug two SFP modules in, connect them together with cable, and run IBERT for 7 Series GTP Transceiver’s example design. Note that when Creating Links and Link Groups, you’ll need to establish a link between MGTPTX0_216 and MGTPRX1_216 or MGTPTX1_216 and MGTPRX0_216 (one SFP lane being the TX and the other the RX). Then you could capture some eye diagrams and validate sent and received data.
Additionally, using the same physical SFP configuration above, you could check out Aurora 8B/10B’s example design.
I’m sure Opal Kelly would be willing to address your concerns. Reach out to them at [email protected]
We have flagged your response as inappropriate for this public forum. Michael was simply trying to be helpful in offering some additional references you may want to look into. Your response was disparaging and disrespectful.
As you’ve noted, there are a lot of different combinations of Vivado version, module, protocol, and physical layer supported by the FPGA transceivers. This flexibility is why the number of pages in the FPGA documentation numbers in the hundreds, if not thousands, of pages.